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Manu Awasthi

Associate Professor of Computer Science, Ashoka University

Ph.D. University of Utah

Prof. Awasthi earned his PhD in Computer Science from the University of Utah and a Bachelor of Technology in Computer Science and Engineering from IIT(BHU) Varanasi.

Before joining Ashoka, Prof. Awasthi was with the Department of Computer Science and Engineering at IIT Gandhinagar. Prior to that, he spent two years with Micron’s  Architecture Definition Group (ADG) in Boise, ID and three years with Samsung’s Memory Solution Lab in San Jose, CA, where he was involved in R&D, evaluation and prototyping of next generation memory and storage systems. He has served on program committees of many conferences, was awarded the Early Career Research Award (ECRA) by Science and Education Research Board (SERB), a Research Fellowship by IIT Gandhinagar and a Teaching Fellowship by the University of Utah. He is the co-author of two best paper award winning publications.

Prof. Awasthi is primarily interested in problems involving design of computer systems and associated trade-off analysis at multiple levels of the computing stack including architecture, system software, programming languages and large scale computing deployments. In the recent past, his work has revolved around multiple aspects of system design – from workload characterization, to design and optimization of memory and storage hierarchies, to proposing, evaluating and optimizing novel system-level architectures and non-traditional computing paradigms for a wide variety of computing devices and workloads.

Journal

  1. Zero Aware Configurable Data Encoding by Skipping Transfer for Error Resilient Applications, Chandan Kumar Jha, Shreyas Singh, Riddhi Thakker, Manu Awasthi, Joycee Mekie, IEEE Transactions on Circuits and Systems I: Regular Papers, May 2021
  2. Fixed-Posit: A Floating-Point Representation for Error-Resilient Applications, Varun Gohil, Sumit Walia, Joycee Mekie, Manu Awasthi, IEEE Transactions on Circuits and Systems II: Express Briefs, April 2021
  3. I/O Workload Management for All-Flash Datacenter Storage Systems Based on Total Cost of Ownership, Zhengyu Yang, Manu Awasthi, Mrinmoy Ghosh, Janki Bhimani, Ningfang Mi, IEEE Transactions on Big Data, September 2018
  4. Docker Container Scheduler for I/O Intensive Applications running on NVMe SSDs, Janki Bhimani, Zhengyu Yang, Ningfang Mi, Jingpei Yang, Qiumin Xu, Manu Awasthi, Rajinikanth Pandurangan, Vijay Balakrishnan, IEEE Transactions on Multi-Scale Computing Systems, Vol. PP, No. 99, 2018, Issue 1
  5. Managing Data Placement in Systems with Multiple Memory Controllers, Manu Awasthi, David Nellans, Kshitij Sudan, Rajeev Balasubramonian, Al Davis, International Journal of Parallel Programming (IJPP), February, 2012, Volume 40, Issue 1
  6. Understanding the Impact of 3D Stacked Layouts on ILP, Manu Awasthi, Vivek Venkatesan, Rajeev Balasubramonian, Journal of Instruction Level Parallelism (JILP), Volume 7, 2007

Conferences and Workshops

  1. ANSim: A Fast and Versatile Asynchronous Network-On-Chip Simulator, Tom Glint, Jitesh Sah, Manu Awasthi, Joycee Mekie, IEEE International Conference on Computer Design (ICCD ‘20), October, 2020
  2. Prefetching in Hybrid Main Memory Systems, Subisha V, Varun Gohil, Nisarg Ujjainkar, Manu Awasthi, USENIX Workshop on Hot Topics in Storage and File Systems (HotStorage ‘20), July, 2020
  3. Efficacy of Statistical Sampling on Contemporary Workloads: The Case of SPEC CPU2017, Sarabjeet Singh, Manu Awasthi, IEEE International Symposium on Workload Characterization (IISWC ‘19), Orlando, November 2019
  4. FAB: Framework for Analyzing Benchmarks, Varun Gohil, Shreyas Singh, Manu Awasthi, 10th International Conference on Conference on Performance Engineering, (ICPE ‘19), Work-in-Progress Track, Mumbai, April 2019
  5. Memory Centric Characterization and Analysis of SPEC CPU2017 Suite, Sarabjeet Singh, Manu Awasthi, 10th International Conference on Conference on Performance Engineering, (ICPE ‘19), Mumbai, April 2019. (arXiv version with more details)
  6. META: Memory Exploration Tool for Android Devices24th International Conference on Mobile Computing and Networking, (MobiCom ‘18), Poster Track, New Delhi, October 2018
  7. Exploring Non-Volatile Main Memory Architectures for Handheld Devices, Sneha Ved, Manu Awasthi IEEE Conference on Design Automation and Test in Europe, (DATE), Dresden, March 2018
  8. Rack Level Scheduling for Containerized Workloads, Qiumin Xu, Krishna T. Malladi, Manu Awasthi, 12th International Conference on Networking, Architecture, and Storage (NAS) Poster Track, Shenzhen. August 2017
  9. Performance Analysis of Containerized Applications on Local and Remote Storage, Qiumin Xu, Manu Awasthi, Krishna T. Malladi, Janki Bhimani, Jingpei Yang, Murali Annavaram, 33rd International Conference on Massive Storage Systems and Technology (MSST), Santa Clara. May 2017
  10. Docker Characterization on High Performance SSDs, Qiumin Xu, Manu Awasthi, Krishna T. Malladi, Janki Bhimani, Jingpei Yang, Murali Annavaram, 18th International Symposium on Performance Analysis of Systems and Software (ISPASS), Poster Track, San Francisco Bay Area. April 2017
  11. KOVA : A Tool for Kernel Visualization and Analysis, Manu Awasthi, Krishna T. Malladi, 35th International Performance Computing and Communications Conference (IPCCC), Luxembourg. December 2016
  12. Understanding Performance of I/O Intensive Containerized Applications for NVMe SSDs, Janki Bhimani, Jingpei Yang, Zhengyu Yang, Ningfang Mi, Qiumin Xu, Manu Awasthi, Rajinikanth Pandurangan, Vijay Balakrishnan, 35th International Performance Computing and Communications Conference (IPCCC), Luxembourg. December 2016
  13. FlexDrive: A Framework to Explore NVMe Storage Solutions, Krishna T. Malladi, Manu Awasthi, Hongzhong Zheng, 18th International Conference on High Performance Computing and Communications (HPCC), Sydney, Australia. December 2016
  14. A Fresh Perspective on Total Cost of Ownership Models for Flash Storage in Datacenters, Zhengyu Yang, Manu Awasthi, Mrinmoy Ghosh , Ningfang Mi, 8th International Conference on Cloud Computing Technology and Science (CloudCom), Luxembourg, December 2016
  15. DRAMPersist: Making DRAM Systems Persistent, Krishna T. Malladi, Manu Awasthi, Hongzhong Zheng, 2nd International Conference on Memory Systems (MEMSYS), Washington DC, October 2016
  16. DDRAMScale: Mechanisms to increase DRAM Capacity, Krishna T. Malladi, Uksong Kang, Manu Awasthi, Hongzhong Zheng, 2nd International Conference on Memory Systems (MEMSYS), Washington DC, October 2016
  17. Software-Defined Emulation Infrastructure for High Speed Storage, Krishna T. Malladi, Manu Awasthi, Hongzhong Zheng, 9th International Systems and Storage Conference (SYSTOR), Haifa, June 2016
  18. Rethinking Design Metrics for Datacenter DRAM, Manu Awasthi, 1st International Conference on Memory Systems (MEMSYS), Washington DC, October 2015
  19. Performance Analysis of NVMe SSDs and their Implication on Real World Databases, Qiumin Xu, Huzefa Siyamwala, Mrinmoy Ghosh, Manu Awasthi, Tameesh Suri, Zvika Guz, Anahita Shayesteh, Vijay Balakrishnan, ACM SIGMETRICS, Portland, June 2015
  20. Performance Characterization of Hyperscale Applications on NVMe SSDs, Qiumin Xu, Huzefa Siyamwala, Mrinmoy Ghosh, Tameesh Suri, Manu Awasthi, Zvika Guz, Anahita Shayesteh, Vijay Balakrishnan, 8th International Systems and Storage Conference (SYSTOR), Israel, May 2015
  21. *Performance Characterization of Realistic Hyperscale Applications on NVMe SSDs, Qiumin Xu, Mrinmoy Ghosh, Manu Awasthi, Tameesh Suri, Zvika Guz, Anahita Shayasteh, Vijay Balakrishnan, 6th Annual Non-Volatile Memories Workshop (NVMW), Poster Track, San Diego, March 2015
  22. System Level Characterization of Datacenter Applications, Manu Awasthi, Tameesh Suri, Zvika Guz, Anahita Shayesteh, Mrinmoy Ghosh, Vijay Balakrishnan, 6th International Conference on Performance Engineering (ICPE) (Best Paper Award), Austin, February 2015
  23. Real-Time Analytics as the Killer Application for Processing-In-Memory, Zvika Guz, Manu Awasthi, Vijay Balakrishnan, Mrinmoy Ghosh, Anahita Shayesteh, Tameesh Suri, 2nd Workshop on Near-Data Processing (WoNDP @ MICRO), Cambridge, December 2014
  24. Efficient Scrub Mechanisms for Error-Prone Emerging Memories, Manu Awasthi, Manjunath Shevgoor, Kshitij Sudan, Bipin Rajendran, Rajeev Balasubramonian, Viji Srinivasan, 18th International Symposium on High Performance Computer Architecture (HPCA), New Orleans, February 2012
  25. Prediction Based DRAM Row-Buffer Management in the Many-Core Era20th International Conference on Parallel Architecture and Compilation Techniques (PACT), Manu Awasthi, David W. Nellans, Rajeev Balasubramonian, Al Davis, Poster Track, Galveston Island, October 2011
  26. Handling PCM Resistance Drift with Device, Circuit, Architecture, and System Solutions, Manu Awasthi, Manjunath Shevgoor, Kshitij Sudan, Rajeev Balasubramonian, Bipin Rajendran, Viji Srinivasan, 2nd Non-Volatile Memories Workshop (NVMW), San Diego, March 2011
  27. Handling the Problems and Opportunities Posed by Multiple On-Chip Memory Controllers, Manu Awasthi, David Nellans, Kshitij Sudan, Rajeev Balasubramonian, Al Davis, 19th International Conference on Parallel Architecture and Compilation Techniques (PACT) (Best Paper Award), Vienna, September 2010
  28. Increasing DRAM Efficiency with Locality-Aware Data Placement, Kshitij Sudan, Niladrish Chatterjee, David Nellans, Manu Awasthi, Rajeev Balasubramonian, Al Davis, 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Pittsburgh, March 2010
  29. Dynamic Page Placement to Manage Capacity, Replication, and Sharing within Large Caches, Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonian, John Carter, 15th International Conference on High Performance Computer Architecture (HPCA), Raleigh, February 2009
  30. Scalable and Reliable Communication for Hardware Transactional Memory, Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian, 17th International Conference on Parallel Architectures and Compilation Techniques (PACT), Toronto, October 2008
  31. *Exploring the Design Space for 3D Clustered Architectures, Manu Awasthi, Vivek Venkatesan, Rajeev Balasubramonian, 3rd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac2), Yorktown Heights, October 2006.

Technical Reports

  1. USIMM: the Utah SImulated Memory Module, Niladrish Chatterjee, Rajeev Balasubramonian, Manjunath Shevgoor, Seth H. Pugsley, Aniruddha N. Udipi, Ali Shafiee, Kshitij Sudan, Manu Awasthi, Zeshan Chishti, School of Computing, University of Utah Technical Report UUCS-12-002, February 2012
  2. Scalable, Reliable, Power-Efficient Communication for Hardware Transactional Memory, Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian, School of Computing, University of Utah Technical Report UUCS-08-001, January 2008

Thesis

  1. Managing Data Locality in Future Memory Hierarchies Using a Hardware Software Codesign Approach, Manu Awasthi, University of Utah PhD Dissertation, December 2014.
Study at Ashoka

Study at Ashoka